Description
PULPcontroller is an open-source HW/SW prototype for on-chip power management of HPC processors. It is developed as part of the European-Processor-Initiative (EPI) by UNIBO. It is composed by an open-source RISC-V HW design and an open-source firmware which implements the power capping, thermal management services as well as the interface with the operating system and with the Board Management Controller Firmware. The first realization of the PULPcontroller will be in the RheaR1 EPI chip. Thanks to its open design and flexible architecture, it can also serve as firmware level node manager.
Integration
The PULPcontroller communicates with physical buses and shared memory regions with the BMC and with the operating system, implementing both the in-band and the out-of-band communication channel with the node-manager, the job manager, the monitoring system and the resource manager. Additional interfaces will be provided to improve the performance of the REGALE tools in the future European Low Power Processor.
Sophistication
The PULPcontroller is designed to allow the execution of complex algorithm (machine- learning/signal processing) on fine-grain on-chip and off-chip telemetry. By interfacing with the REGALE tools and embedding part of their services and algorithm, their overheads can be drastically reduced. Through these new interfaces the PULPcontroller algorithms will be enhanced with application awareness and thermal and power capping based on predictive models tuned in the target HW.